1. Field of the Invention
The present invention relates generally to processes for semiconductor manufacturing and, more particularly, to modeling, measuring, characterizing, and controlling overlay and focusing errors associated with scanning projection systems used in ULSI photolithography.
2. Description of the Related Art
General
It is very likely that sub-50 nm lithographic processing will require extremely tight layer-to-layer overlay tolerances to meet next generation device performance requirements (see, for example, “2001 ITRS Roadmap”, SEMATECH, pp. 1–21). Overlay registration on critical layers can directly impact device performance, yield, and repeatability. A typical microelectronic device or circuit can frequently include more than twenty levels or pattern layers. The placement of patterned features on each of the levels must match the placement of corresponding features on other levels—called overlap—within an accuracy that is some fraction of the minimum feature size or critical dimension (CD). Overlay error is typically, although not exclusively, measured with a metrology tool that is appropriately called an overlay tool, using several techniques (see, for example, “Semiconductor Pattern Overlay”, N. Sullivan, SPIE Critical Reviews, Vol. CR52, pp. 160–188). The terms “overlay metrology tool” and “overlay tool” are used to mean any tool capable of determining the relative position of two alignment attributes that are separated within 2000 um (microns) of each other. The importance of overlay error and its impact to yield is known and is described elsewhere (see, for example, “Measuring Fab Overlay Programs”, R. Martin et al., SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, pp. 64–71, March 1999, and “A New Approach to Correlating Overlay and Yield”, M. Preil et al., SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, pp. 208–216, March 1999). Lithographers have created statistical computer algorithms (for example, Klass II, “Lens Matching and Distortion Testing in a Multi-Stepper, Sub-Micron Environment”, A. Yost et al., SPIE, Vol. 1087, pp. 233–244, 1989; and Monolith, “A Computer Aided Engineering Workstation for Registration Control”, E. McFadden et al., SPIE, Vol. 1087, pp. 255:266, 1989) that attempt to quantify and divide overlay error into repeatable or systematic and non-repeatable or random effects (see, for example, “Matching of Multiple Wafer Steppers for 0.35 Micron Lithography Using Advanced Optimization Schemes”, M. van den Brink et al., SPIE, Vol. 1926, pp. 188:207, 1993; “A Computer Aided Engineering Workstation for Registration Control”, supra; “Semiconductor Pattern Overlay”, supra; and “Machine Models and Registration”, T. Zavecz, SPIE Critical Reviews, Vol. CR52, pp. 134–159). An overall theoretical review of overlay modeling can be found in “Semiconductor Pattern Overlay”, supra. Overlay error is typically divided into the following two major categories. The first category, called inter-field or grid overlay error, is concerned with the actual position of the translation and rotation or yaw of the image field as recorded in the photoresist on a silicon wafer using an exposure tool, i.e., stepper or scanner (see FIG. 1). The second category, called intra-field overlay error, is the positional offset of an individual point inside a field referenced to the nominal center of an individual exposure field (see FIG. 1). Intra-field overlay errors are generally composed of lens aberrations or distortions, scanning irregularities, and reticle alignment.
It should be noted that most overlay measurements are made on silicon product wafers after each photolithographic process, prior to final etch. Product wafers cannot be etched until the photoresist target patterns are properly aligned to the underlying target patterns. See “Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology”, J. Pellegrini, SPIE, Vol. 3677, pp. 72–82. Manufacturing facilities generally rely heavily on exposure tool alignment and calibration procedures to help insure that the scanner tools are aligning properly. See, for example, “Stepper Matching for Optimum Line Performance”, T. Dooly et al., SPIE, Vol. 3051, pp. 426–432, 1997; “Mix-and-Match: A Necessary Choice”, R. DeJule, Semiconductor International, pp. 66–76, February 2000; and “Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure”, M. van den Brink et al., SPIE, Vol. 921, pp. 180–197, 1988. Inaccurate overlay modeling algorithms can corrupt the exposure tool calibration procedures and degrade the alignment accuracy of the exposure tool system. See “Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology”, supra.
Finally, while overlay error measures the x and y positional alignment of patterned features in reference to other layers, focusing error (z positional error) typically reduces image fidelity and changes the effective magnification of the photolithographic imaging system. While some techniques use focusing errors (chromatic enhancements) to attempt to improve the overall lithographic depth of focus (see, for example, “Method and Apparatus for Enhancing the Focus Latitude in Lithography”, Pei-Yang Yan, U.S. Pat. No. 5,303,002 issued Apr. 12, 1994), unintentional and uncorrected focus error reduces both image fidelity and the lithographic process window (see, for example, “Comprehensive Guide to Optical Lithography Simulation”, C. Mack, FINLE Technologies, Inc., 2nd ed., 1997). Typically one uses the term focal plane deviation (FPD) to measure the extent of lens or system dependent focal error over the entire lithographic imaging field, lithographic systems with low to moderate amounts of focal plane deviation typically image better than those with gross amounts of focal plane deviation. Typically, the focal plane deviation associated with a photolithographic stepper or scanner is measured with some type of special lithographic imaging technique using special reticle or mask patterns. See “Distinguishing Dose from Defocus for In-Line Lithography Control”, C. Ausschnitt, SPIE, Vol. 3677, pp. 140–147, 1999; “Understanding Optical End of Line Metrology”, D. Ziger et al., SPIE Optical Eng., Vol. 39(07), pp. 1951–1957, 2000; “Controlling Focal Plane Tilt”, S. Hsu et al., Semiconductor International, Apr. 1, 1999 (available via Internet at the URL of [www.reed-electronics.com/semiconductor/toc/4%2F1%2F1999]) and “Focus Monitor for Alternating Phase Shift Masks”, L. Liebmann et al., U.S. Pat. No. 5,936,738 issued Aug. 10, 1999.
While some focusing error is usually due to lens aberration, some is due to stage non-flatness, stage tilt, wafer tilt, wafer surface irregularities, and scanner noise. Traditional methods tend to estimate the overall magnitude of FPD but fail to account for scanner noise. In addition, most techniques cannot separate the FPD error into systematic and random portions (see, for example, “Controlling Focal Plane Tilt”, supra)—which is important for process control applications.
General Overview of Control Theory
Important aspects of control theory and methods related to semiconductor process control will next be briefly reviewed in relatively general terms. The idea of controlling a process or event is typically described in one of two ways: classical or modern. See, for example, “Feedback Control of Dynamic Systems”, G. Franklin et al., Addison Wesley Pub., p. 312, 1986. The term classical is generally used for those methods typically employing transfer-function based control algorithms. Modem control theory typically refers to those methods employing state-space control design and is quite suited for numerical techniques.
As semiconductor microprocessors have become more complex, so to are the methods for controlling the processes to fabricate them. In fact, advances in semiconductor process control—especially those related to photolithography—are vital in keeping manufacturing costs down, increasing transistor density, and improving overall circuit (microprocessor, DRAM, etc.,) and device (transistor) performance. See, for example, “2001 ITRS Roadmap”, supra. Since photolithography and the photolithographic exposure tools (steppers and scanners) typically account for the largest portion of semiconductor manufacturing costs—due to machine costs and process complexity—it is important that the semiconductor industry continues to explore new methods for controlling and improving the lithographic process. Modern control methods, especially those methods of Kalman (see, for example, “Applied Optimal Control and Estimation”, F. L. Lewis, Prentice-Hall, Chapter 1, 1992) that focus on dynamic behavior in the presence of noise disturbance, are very well suited for controlling the dynamic behavior of lithographic scanners. In fact, in control theory, Kalman formalized the notion of optimality in control theory by minimizing a very general quadratic generalized energy function. In estimation theory, Kalman introduced stochastic notions that applied to non-stationary time-varying systems, thus providing a recursive solution, the Kalman filter, for the least-squares approach first used by C. F. Gauss (1777–1855) in planetary orbit estimation. The Kalman filter is the natural extension of the Wiener filter to non-stationary stochastic systems. See, for example, “Applied Optimal Control and Estimation”, supra.
Over the past thirty-some years, the microelectronics industry has experienced dramatic rapid decreases in critical dimension by constantly improving photolithographic imaging systems. Today, these photolithographic systems are pushed to performance limits. As the critical dimensions of semiconductor devices approach 50 nm, the overlay error requirements will soon approach atomic dimensions while the useable depth of focus will be reduced to <100 nm. See, for example, “Life Beyond Mix-and-Match: Controlling Sub-0.18 Micron Overlay Errors”, T. Zavecz et al., Semiconductor International, July 2000, pp. 205–214; and “2001 ITRS Roadmap”, supra. To meet the needs of next generation device specifications, new overlay and focus monitoring/control methodologies will need to be developed. In particular, overlay and focus monitoring/control methodologies that can accurately separate systematic and random effects and break them into assignable causes will greatly improve device process yields. See, for example, “A New Approach to Correlating Overlay and Yield”, supra and “Controlling Focal Plane Tilt”, supra. In particular, new overlay and focus methodologies that can be implemented into advanced process control or automated control loops will likely be most important. See “Comparisons of Six Different Intra-Field Control Paradigms in an Advanced Mix and Match Environment”, J. Pellegrini, SPIE, Vol. 3050, pp. 398–406, 1997; “Characterizing Overlay Registration of Concentric 5× and 1× Stepper Exposure Fields Using Inter-Field Data”, F. Goodwin et al., SPIE, Vol. 3050, pp. 407–417, 1997; and U.S. Pat. No. 5,303,002 to Yan, supra. Finally, another area where quantifying and correcting overlay error is of vital concern is in the production of next generation EUVL and EPL masks or reticles. See “2001 ITRS Roadmap”, supra.
Thus, the continuous reduction in semiconductor feature size and improved circuit functionality continues to force semiconductor manufacturing facilities to develop ingenious methods to help contain skyrocketing fabrication costs—especially those associated with photolithography where reductions in image fidelity, positional alignment, and the lithographic process window can halt all development and production activities. Going forward, new methods for monitoring and controlling systematic overlay and focusing errors will help speed product ramp, drive down development costs, and improve product yields.